Computers are known to include a central processing unit, video processing circuitry, audio processing circuitry, and input/output ports to interface with peripheral devices. Such peripheral devices include a display such that applications being executed by the central processing unit may be visible to the computer user. The object, or image, elements being displayed are generated by, or caused to be generated by, the central processing unit and provided to the video processing circuitry. The video processing circuitry renders the object, or image, elements into pixel data wherein the pixel data is provided to the display.
As part of the processing of object, or image, elements, the video graphic circuitry stores the pixel data in memory, which is often referred to as a frame buffer. Typically, each entry in the frame buffer will correspond to a pixel location on the display. For example, for a 640.times.480 pixel display, the first entry of memory will correspond to pixel location (0,0), the second memory location to pixel (1,0), the third to pixel location (2, 0), etc. As such, the first 640 entries in the memory correspond to the first line of the display. The second 640 entries in the memory correspond to the second line of the display, the third 640 entries in memory correspond to the third line, etc.
While linearly mapping the physical pixel locations to the memory locations provides a straightforward implementation, there are certain drawbacks. For example, when objects are being rendered by the video processing circuit the objects typically occupy more than one line. In other words, the objects being rendered have an X value greater than 1 and a Y value greater than one. To render such an object when linear mapping is used, each line containing pixel data for the object would need to be retrieved from memory. To improve the efficiency of data retrieval from memory, pipeline memory retrieval circuitry may be used, such that pixel data is retrieved with each clock cycle. However, the pipeline process only works when a particular line, which is often referred to as a page, is being retrieved. When a subsequent page needs to be retrieved, it takes seven clock cycles to fill the pipe and to set the buffers. Thus, to render a triangle that has an X value of 10 and a Y value of 10, 120 cycles are required. Of the 120 cycles, fifty are required to retrieve the pixel data for the 50 pixels of the triangle, while 70 cycles are required to jump to the next page. Thus, data is being retrieved at 2.4 clocks per pixel.
To reduce the latency in the linear mapping, the memory may be arranged in tiles. By tiling the memory, there is no longer a linear relationship between the pixel locations and addresses within the memory. Each tile corresponds to a block of physical pixel locations of the display, where, within the tile, the addresses map linearly to the pixel location within the tile. For example, the first 640 entries in the memory may correspond to a block on the physical display of 10 lines of the first 64 pixels. In other words, pixel location (0, 0) through pixel location (64, 0); pixel location (0, 1) through (63,1); up to pixel location (0, 9) through pixel location (63, 9) are included in this tile and occupy the first 640 entries in the frame buffer. Thus, with tiled grouping, when an object falls within a particular tile on the display, only one page is required to render the object. If however, the object occupies more than one tile, the latency from retrieving the next page is still present.
Therefore, a need exists for a method and apparatus that reduces latency in the retrieval of tiled memory blocks.